1. Field of the Invention
The present invention relates to a data processor operated by a pipeline processing system, and specifically relates to a data processor having a function of processing a POP instruction.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a configuration of a pipeline processing mechanism of a conventional data processor.
The pipeline processing mechanism of the conventional data processor is configurated with an instruction fetch stage 391, an instruction decoding stage 392, an operand address calculation stage 393, an operand fetch stage 394 and an execution stage 395. Then, an instruction is decomposed into a plurality of unit codes (step codes) for pipeline processing in the decoding step, undergoing pipeline processing. The detail of such a data processor is disclosed in the Japanese Patent Application Laid-Open No. 63-89932 (1988).
In the pipeline processing mechanism of the conventional data processor as described above, elements configurating a pipeline are divided between portions for pre-processing such as the instruction fetch stage 391, the instruction decoding stage 392, the operand address calculation stage 393 and the operand fetch stage 394 and a portion for executing an instruction such as the execution stage 395.
The portions for pre-processing only perform pre-processing relating to an operand designated in the instruction. Then, the instruction is executed in the execution stage 395 using the operand prepared by the pre-processing.
However, in such a data processor, an instruction, in which only one operand designating part is included but other operands are required by instruction function, is performed no sufficient pre-processing on the pipeline.
For an example of such an instruction, a POP instruction is considered. The POP instruction enables a memory or register to be designated as a destination. In the data processor, normally, a stack for retreating data is formed in a memory space. Then, an instruction for retreating data in the stack and an instruction for reading the retreated data from the stack are provided. The former instruction is so called the PUSH instruction, and the latter instruction is so called the POP instruction respectively, and these instructions are symmetrical each other. In addition, a stack pointer (SP) indicates the address of the highest order (stack top) of the stack all the time.
The POP instruction is a one-operand instruction having only one operand for designating destination. However, as to the function of the instruction itself, the POP instruction actually is a two-operand instruction implying that a source operand is the stack top, and is equivalent to a transfer instruction between memory and memory or between memory and register.
In processing the POP instruction, on the pipeline of the conventional data processor, only a step code for processing destination is generated by a destination designating part of the POP instruction. The processing of this step code refers to performing address calculation of destination in the operand address calculation stage 393 which is a portion pre-processing an instruction. Since the POP instruction has no designating part of source operand, the step code relating to the source is not generated, and the preprocessing relating to the source designating part is not performed at all.
The processing relating to the source designating part is executed in the execution stage 395 which is a portion executing the instruction by a series of micro instructions when the POP instruction is executed. Specifically, in the processing relating to a source operand of POP instruction at the execution stage 395, first the data is fetched from the stack top and the fetched data is transferred to the destination address prepared pre-processing.
In performing such a processing, the processing relating to the source designating part to be performed as a preprocessing in a normal two-operand instruction is performed in the execution stage 395, and therefore the processing load of the execution stage 395 is very heavy. Also, unevenness of processing load in each stage takes place, and therefore a reduction in the processing efficiency of the pipeline processing is brought on.
In the conventional data processor, as described above, the POP instruction is processed in the pipeline processing mechanism. At this time, the execution stage itself is required to perform the processing of fetching the operand from the stack top, and therefore the load of data processing in the stage executing the instruction becomes larger in comparison with the pre-processing stages, and therefore a problem exists that the processing efficiency of the POP instruction is not improved.